The hottest trend of parallel design FPGA and PCB

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The trend of parallel design FPGA and PCB system design

the increasing complexity of system design requires the design of high-performance FPGA and PCB to be carried out in parallel. By integrating FPGA and PCB design tools and adopting advanced manufacturing processes such as high-density interconnection (HDI), this design method can reduce the system cost, optimize the system performance and shorten the design cycle

Figure 1 FPGA and PCB design teams must work in parallel, constantly exchanging data and information to ensure the success of system design

the driving force behind the electronic industry is the demand for faster and cheaper products and bringing products to the market before competitors. The progress of IC technology has always been one of the main factors to promote the increase of function and performance, and FPGA technology has been developing at a very fast speed. Unlike in the past, FPGA was only used as glue logic, now FPGA has been used to realize the main system functions. The number of logic gates of FPGA has reached 10million, and the core speed has reached 400MHz, which can provide the next generation of inter chip communication speed of up to 11gbps. At the same time, it still maintains a very reasonable cost. Therefore, compared with ASIC and custom IC, FPGA is a more attractive choice

the effect of the progress of IC and FPGA technology on downstream industries has affected the PCB industry. These senior executives' pin count and high-performance packaging promote the new PCB production and design technology to have functions such as embedded passive components, thousands of megabits of signal and EMI analysis, and put forward the demand for special high-density and high-performance wiring. The basic system design method is also changing. The design of FPGA and PCB can be carried out in parallel to reduce the system cost, optimize the system performance and shorten the design cycle

PCB and FPGA are generally created in different design environments. In the past, these design schemes rarely communicated with each other. However, with the increasing popularity of high-performance and high-density FPGA devices, in order to meet the tight market schedule, PCB and FPGA design teams must work in parallel (see Figure 1), constantly exchanging data and information to ensure the success of the whole system design

when implementing high-end FPGA on PCB, design engineers face the dual challenges of performance optimization and system design productivity. Design engineers must ask themselves: what is the problem that slows down the process? What needs to be done to get the best performance? The answers to these questions can help them identify solutions that can achieve smaller, cheaper and faster systems

challenge of design efficiency

when design engineers need to design PCB and FPGA in parallel, FPGA design engineers can no longer design independently as before, and then hand over the completed FPGA design to PCB design engineers. A competitive design requires FPGA and PCB design engineers to cooperate from top to bottom and make some compromises to ensure that an optimal system is finally obtained. The advantage of concurrent design is that it can reduce the design cycle, optimize the system performance and reduce the manufacturing cost

the challenge of parallel design is that the results obtained by FPGA layout and wiring tools need to be accurately and quickly mapped to the schematic and PCB layout. At the same time, any changes in PCB design must also be updated on FPGA. The traditional design process is to design FPGA first, and then hand them over to PCB design engineers for circuit board implementation. Now this practice is no longer feasible

if FPGA design/synthesis, layout/wiring and PCB design environment are not integrated, the communication between FPGA and PCB schemes must be realized manually. This may be acceptable for small FPGAs with hundreds of pins, but many designs now have multiple highly complex FPGAs. Using this method to communicate information will be very time-consuming and error prone. Just the creation and update of PCB schematic symbols of high-level pin count FPGA can highlight this problem (see Figure 2 for the evaluation of design time)

Figure 2 Estimation of the time required to create and update PCB schematic symbols of FPGAs

another problem involves large FPGAs on PCBs. Unlike the small FPGA symbols attached to the collet, a single symbol of a large FPGA cannot be placed in a schematic diagram. These symbols must be divided into several symbols through functional grouping and remain unchanged during the iterative process of FPGA design

fpga design engineers spend a lot of time adjusting performance and selecting the correct i/o pin driver/receiver. However, FPGA design is not only controlled by FPGA design engineers. When the demand for lightweight automobile will be further improved. When FPGA layout and wiring are carried out on PCB, the design environment may require changing the pin allocation of FPGA. If there are no FPGA design rules in PCB tools, this may become a repeated and time-consuming process

in addition, the i/o allocation of FPGA has also become a systematic problem. Design tools need to be able to manage pin assignments, but they must be used by PCB and FPGA design engineers to communicate pin constraints. PCB design engineers cannot create a condition that prevents FPGA timing convergence, and FPGA design engineers cannot create a condition that prevents system timing convergence

the examples given in Figure 3 and Figure 4 reflect the wiring before and after the performance optimization of the FPGA assembled on the PCB. The 32-bit bus of FPGA must communicate directly with the left connector. This is a high-speed bus, and all the networks on it must be matched to obtain appropriate skew control

in Figure 3, in order to match all the routing lengths with the longest network, the router adds a lot of serpentine routing. From the perspective of PCB wiring, the result is a mess: there are a lot of extra congestion, too many extra cabling, and a bus with suboptimal performance

Figure 3 wiring diagram before FPGA performance optimization

in Figure 4, the router also matches all routing lengths with the longest routing. Even so, the length of each cable is only 1.8 inches, compared with 3.2 inches previously. The shorter matching length reduces the bus delay to 320 picoseconds. This performance optimization is the result of integrating the FPGA and PCB design process, which can obtain an ideal FPGA pin diagram

Figure 4 wiring diagram after FPGA performance optimization

this example illustrates the possible challenges of assembling FPGA on PCB, including: additional congestion requires longer PCB design time to complete wiring; Not the optimal system performance; Additional wiring requires additional PCB layers, thereby increasing manufacturing costs

performance obstacles in terms of function

ic and FPGA devices have been optimized for higher performance. For example, they can now achieve serial communication performance of several gigabytes per second. From the perspective of timing convergence, signal integrity and overall reduction of PCB wiring density, this method has the following advantages:

(1) timing calibration is not so strict: the clock is contained in the serial signal, so the design engineer does not need to manage the timing between the clock and data

(2) improve signal integrity: all signals use differential line pairs, which can improve signal quality

(3) simplified wiring: serial signals are transmitted along one path (actually a differential line pair), rather than parallel transmission on a bus with multiple routes, which means that interconnection requires less routes and layers

(4) on Chip Termination: by integrating variable resistance terminators in FPGA, less surface mount devices are required on the board, which can save space and improve performance. The updated devices also include on-chip capacitors, which can save more space

using these high-end FPGAs in the system makes PCB design the key to the success of the whole system design, in which the system must be able to run at high speed, be cost-effective, and be designed on time

the communication speed of several gigabytes per second requires a set of new tools that can route and verify signals. At this time, the wiring, connectors and vias on the PCB also need to consume power, so they must be carefully modeled, and the classical signal integrity analysis method is used to calculate the delay, overshoot/undershoot and crosstalk. In addition, the serial connection operating in the GHz frequency range must be modeled with understanding bit pattern, pre emphasis, equalization and eye diagram. EDA and FPGA suppliers are also cooperating to provide accurate device models, design constraints and reference designs in the form of "design kits", which will improve the design quality and shorten the design cycle

serial i/o also requires improved PCB layout and wiring technology driven by common system constraints. In addition, the routing of differential line pairs must be strictly controlled according to the maximum matching delay and the number of vias used

advanced PCB manufacturing technology

another challenge arising from the number and density of high-end FPGAs is the need to assemble FPGAs onto PCBs, and then connect them to other ICs on the board. There are so many pins in a small area that it is almost impossible to make internal wiring using ordinary PCB manufacturing process. As a result, these devices have promoted the adoption of advanced PCB manufacturing technologies, such as high-density interconnection (HDI) and embedded passive devices

hdi uses IC manufacturing technology on PCB. HDI layer deposited on the traditional PCB laminate layer (such as FR4) can produce very narrow routing and small via (micro via), and it is easy to fan out away from high-density packaging, usually ball grid array (BGA) or chip level packaging (CSP). In addition, using these HDI technologies also requires special PCB layout software that can understand this mixed PCB and IC production technology

The advantages of

hdi/micro via include:

reducing product size: the height and thickness of PCB substrate are reduced, and the volume is also reduced

increase the wiring density: each device has more wiring, and the devices are arranged more closely

cost reduction: HDI can reduce the number of layers and area of circuit boards, so that each large bare board can produce more circuit boards and reduce production costs

improve electrical performance: the parasitic effect of HDI is only one tenth of that of through hole, and its lead wire is shorter, with greater noise margin

reduce radio interference (RFI)/emi: because the ground plane is closer to or just at the surface deviation, restart the experimental layer, you can use the distributed capacitance of the ground plane to greatly reduce rfi/emi

improve heat dissipation efficiency: the insulation medium of HDI layer is very thin, and the temperature gradient is very high, which can improve the heat dissipation performance

improve design efficiency: Micro vias make double-sided layout easier, and also improve the routing of device pins (via holes on the pad), thus leaving more inner wiring space

improve the yield (DFM): due to the small gap, HDI board hardly needs to be pressed

reduce the number of layers: generally, surface mount technology (SMT) of 10 to 12 layers is required, and only 6 layers are required for HDI manufacturing process

shorten the design cycle: due to the use of buried holes, the wiring space is more sufficient, which can significantly reduce the design time

in addition, these high-level pin count devices require a lot of decoupling capacitors and termination resistors to ensure working performance. Traditional SMD passive devices will occupy valuable area of the surface layer. By embedding these passive components into the inner layer of PCB, the size of PCB can be greatly reduced and the performance can be improved

embedding passive components has many advantages, including:

increasing design density: moving passive SMD into the inner layer can make other components arranged more closely

reduce the system cost: although additional steps will increase the production cost, the overall system cost can be reduced by reducing SMD and minimizing the circuit board area

reduce the weight of the system and the area of the circuit board: removing SMD can reduce the size of the circuit board

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